VLSI CAD Part II: Layout
You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design.
Monthly Subscription Starting at AED 99 + VAT
- Level Professional
- المدة 24 ساعات hours
- الطبع بواسطة University of Illinois Urbana-Champaign
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Offered by
عن
You should complete the VLSI CAD Part I: Logic course before beginning this course. A modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Recommended Background: Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Elementary knowledge of RC linear circuits (at the level of an introductory physics class).الوحدات
Welcome and Introduction
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- Demographics Survey
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- Welcome and Introduction
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- Syllabus
Tools
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- Two Tools Tutorial
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- Tools For This Course
Week 1 Information
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- Week 1 Overview
ASIC Placement Introduction
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- Basics
- Wirelength Estimation
- Simple Iterative Improvement Placement
- Iterative Improvement with Hill Climbing
- Simulated Annealing Placement
Analytical Placement
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- Analytical Placement: Quadratic Wirelength Model
- Analytical Placement: Quadratic Placement
- Analytical Placement: Recursive Partitioning
- Analytical Placement: Recursive Partitioning Example
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- Week 1 Assignments
Week 2 Information
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- Week 2 Overview
Technology Mapping, Part 1
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- Technology Mapping Basics
- Technology Mapping as Tree Covering
- Technology Mapping—Tree-ifying the Netlist
Technology Mapping, Part 2
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- Technology Mapping—Recursive Matching
- Technology Mapping—Minimum Cost Covering
- Technology Mapping—Detailed Covering Example
Assignments
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- Week 2 Assignments
Problem Set Submission
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- Problem Set #1
Programming Assignment Submission
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Programming
- Programming Assignment #3: Placer
Week 3 Information
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- Week 3 Overview
Basics and Maze Routing
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- Routing Basics
- Maze Routing: 2-Point Nets in 1 Layer
- Maze Routing: Multi-Point Nets
- Maze Routing: Multi-Layer Routing
- Maze Routing: Non-Uniform Grid Costs
Implementation Mechanics and Global Routing
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- Implementation Mechanics: How Expansion Works
- Implementation Mechanics: Data Structures & Constraints
- Implementation Mechanics: Depth First Search
- From Detailed Routing to Global Routing
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- Week 3 Assignments
Problem Set Submission
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- Problem Set #2
Week 4 Information
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- Week 4 Overview
Basics and Logic-Level Timing
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- Basics
- Logic-Level Timing: Basic Assumptions & Models
- Logic-Level Timing: STA Delay Graph, ATs, RATs, and Slacks
- Logic-Level Timing: A Detailed Example and the Role of Slack
- Logic-Level Timing: Computing ATs, RATs, Slacks, and Worst Paths
Interconnect Timing
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- Interconnect Timing: Electrical Models of Wire Delay
- Interconnect Timing: The Elmore Delay Model
- Interconnect Timing: Elmore Delay Examples
Assignments
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- Week 4 Assignments
Problem Set Submission
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- Problem Set #3
Programming Assignment Submission
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Programming
- Programming Assignment #4: Router
Problem Set Submission
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- Problem Set #4
Final Exam
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- Final Exam
End of Course Survey
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- End of Course Survey
Auto Summary
Dive into the complexities of VLSI chip design with "VLSI CAD Part II: Layout," tailored for professionals in Data Science & AI. Under the expert guidance of Coursera, explore the major CAD tools essential for creating ASIC or SoC designs. This course delves into technology mapping, timing analysis, and ASIC placement and routing, emphasizing key logical and geometric representations. Ideal for those with programming experience and a solid foundation in digital design, this 1440-minute course offers both Starter and Professional subscriptions. Elevate your expertise in chip design algorithms and data structures today!
Rob A. Rutenbar