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VLSI CAD Part I: Logic
  • Level Professional
  • Duration 23 hours
  • Course by University of Illinois Urbana-Champaign
  • Offered by

About

A modern VLSI chip has a zillion parts -- logic, control, memory, interconnect, etc. How do we design these complex chips? Answer: CAD software tools. Learn how to build thesA modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called "intellectual property" or IP blocks). How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. Our focus in this first part of the course is on key Boolean logic representations that make it possible to synthesize, and to verify, the gate-level logic in these designs. This is the first step of the design chain, as we move from logic to layout. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Topics covered will include: Computational Boolean algebra, logic verification, and logic synthesis (2-level and multi-level). Recommended Background Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Linear algebra and calculus at the level of a junior or senior in engineering. Exposure to basic VLSI at an undergraduate level is nice -- but it's not necessary. We will keep the course self-contained, but students with some VLSI will be able to skip some background material.e tools in this class.

Modules

Welcome and Introduction

    • 1 Videos
    • 1 Readings
    • 1 Plugin
    • 1 Assignment
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1 Assignment

  • Demographics Survey

1 Videos

  • Welcome and Introduction

1 Readings

  • Syllabus

Tools

    • 1 Readings
    • 4 Programming
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4 Programming

  • KBDD
  • MiniSat
  • Espresso
  • SIS

1 Readings

  • Tools For This Course

Week 1 Information

    • 1 Readings
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1 Readings

  • Week 1 Overview

Computational Boolean Algebra

    • 4 Videos
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4 Videos

  • Computational Boolean Algebra: Basics
  • Computational Boolean Algebra: Boolean Difference
  • Computational Boolean Algebra: Quantification Operators
  • Computational Boolean Algebra: Application to Logic Network Repair

Computational Boolean Algebra: Recursive Tautology

    • 2 Videos
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2 Videos

  • Computational Boolean Algebra: Recursive Tautology
  • Computational Boolean Algebra: Recursive Tautology—URP Implementation

Assignments

    • 1 Readings
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1 Readings

  • Week 1 Assignments

Week 2 Information

    • 1 Readings
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1 Readings

  • Week 2 Overview

BDDs

    • 4 Videos
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4 Videos

  • BDD Basics, Part 1
  • BDD Basics, Part 2
  • BDD Sharing
  • BDD Ordering

SAT

    • 3 Videos
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3 Videos

  • Satisfiability (SAT), Part 1
  • Boolean Constraint Propagation (BCP) for SAT
  • Using SAT for Logic

Assignments

    • 1 Readings
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1 Readings

  • Week 2 Assignments

Problem Set Submission

    • 1 Assignment
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1 Assignment

  • Problem Set #1

Programming Assignment Submission

    • 1 Programming
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1 Programming

  • Programming Assignment #1: Unate Recursive Complement

Week 3 Information

    • 1 Readings
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1 Readings

  • Week 3 Overview

2-Level Logic

    • 3 Videos
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3 Videos

  • 2-Level Logic: Basics
  • 2-Level Logic: The Reduce-Expand-Irredundant Optimization Loop
  • 2-Level Logic: Details for One Step: Expand

Multilevel Logic

    • 5 Videos
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5 Videos

  • Multilevel Logic and the Boolean Network Model
  • Multilevel Logic: Algebraic Model for Factoring
  • Multilevel Logic: Algebraic Division
  • Multilevel Logic: Role of Kernels and Co-Kernels in Factoring
  • Multilevel Logic: Finding the Kernels

Assignments

    • 1 Readings
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1 Readings

  • Week 3 Assignments

Problem Set Submission

    • 1 Assignment
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1 Assignment

  • Problem Set #2

Week 4 Information

    • 1 Readings
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1 Readings

  • Week 4 Overview

Mulitlevel Logic and Divisor Extraction

    • 3 Videos
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3 Videos

  • Mulitlevel Logic and Divisor Extraction—Single Cube Case
  • Mulitlevel Logic and Divisor Extraction—Multiple Cube Case
  • Multilevel Logic and Divisor Extraction—Finding Prime Rectangles & Summary

Don't Cares

    • 5 Videos
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5 Videos

  • Multilevel Logic—Implicit Don't Cares, Part 1
  • Multilevel Logic—Implicit Don't Cares, Part 2
  • Multilevel Logic—Satisfiability Don't Cares
  • Multilevel Logic—Controllability Don't Cares
  • Multilevel Logic—Observability Don't Cares

Assignments

    • 1 Readings
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1 Readings

  • Week 4 Assignments

Problem Set Submission

    • 1 Assignment
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1 Assignment

  • Problem Set #3

Programming Assignment Submission

    • 1 Programming
    • 1 Assignment
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1 Programming

  • Programming Assignment #2: Serious BDDs

1 Assignment

  • Auxiliary Quiz of Serious BDDs

Problem Set Submission

    • 1 Assignment
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1 Assignment

  • Problem Set #4

Final Exam

    • 1 Assignment
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1 Assignment

  • Final Exam

End of Course Survey

    • 1 Plugin
    • 1 Assignment
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1 Assignment

  • End of Course Survey

Auto Summary

Discover the intricate world of VLSI chip design with "VLSI CAD Part I: Logic," a specialized course in the IT & Computer Science domain offered by Coursera. Designed for professionals, this course dives deep into the major design tools used for creating Application Specific Integrated Circuits (ASICs) and System on Chip (SoC) designs. Led by expert instructors, it focuses on the fundamental algorithms and data structures behind key Boolean logic representations essential for synthesizing and verifying gate-level logic. Throughout the course, you'll explore topics such as Computational Boolean algebra, logic verification, and both 2-level and multi-level logic synthesis. The course spans an extensive 1380 minutes, offering a comprehensive learning experience. Ideal candidates are those with programming experience in languages like C, C++, Java, or Python, and a solid understanding of basic digital design, data structures, algorithms, and engineering-level linear algebra and calculus. While prior exposure to VLSI is advantageous, it's not mandatory as the course is structured to be self-contained. Flexible subscription options, including Starter, Professional, and Paid tiers, ensure that you can tailor your learning experience to fit your needs. Join now to gain an in-depth understanding of the tools that power modern VLSI chip design and take your professional skills to the next level.

Rob A. Rutenbar
Instructor

Rob A. Rutenbar