- Level Professional
- Duration 36 hours
- Course by University of Colorado Boulder
-
Offered by
About
This course can also be taken for academic credit as ECEA 5361, part of CU Boulder's Master of Science in Electrical Engineering degree. Hardware Description Languages for Logic Design enables students to design circuits using VHDL and Verilog, the most widespread design methods for FPGA Design. It uses natural learning processes to make learning the languages easy. Simple first examples are presented, then language rules and syntax, followed by more complex examples, and then finally use of test bench simulations to verify correctness of the designs. Lecture presentations are reinforced by many programming example problems so that skill in the languages is obtained. After completing this course, each student will have fundamental proficiency in both languages, and more importantly enough knowledge to continue learning and gaining expertise in Verilog and VHDL on their own.Modules
Introduction to the Course
1
Discussions
- Introduce Yourself
1
Videos
- Introduction to Hardware Description Languages for FPGA Design
1
Readings
- Hardware Description Languages for FPGA Design Assessment Strategy
Lectures
8
Videos
- Why Learn VHDL?
- FPGA Design Flow
- Intro to VHDL: Finite State Machine
- How to speak VHDL, first phrases
- VHDL Assignments, Operators, Types
- VHDL Rules and Syntax, Interface Ports
- VHDL in ModelSim: Download and Install
- VHDL in ModelSim: Adding to your Toolkit
1
Readings
- Misson 2-001: Week 1 Readings
Week 1 Missions
- VHDL 2-bit Comparator
- VHDL Correct Errors
- VHDL Majority Vote
- VHDL 1-bit Full Adder
1
Videos
- Submitting VHDL Programming Assignments
1
Readings
- Files for Week 1 Programming Assignments
2
Quiz
- VHDL Find the Code Errors
- Module 1 Quiz
Lectures
10
Videos
- Learning to speak VHDL (Intro)
- Combinatorial Circuits
- Synchronous Logic: Latches and Flip Flops
- Synchronous Logic: Counters and Registers
- Buses and Tristate Buffers
- Modular Designs: Components, Generate and Loops in VHDL
- Test Benches in VHDL: Combinatorial
- Test Benches in VHDL: Synchronous
- Memory in VHDL
- Finite State Machines in VHDL
1
Readings
- Week 2 Readings
Week 2 Missions
- VHDL 74LS163 Binary Counter
- VHDL Make a Memory
- VHDL Finite State Machine
- VHDL ALU
- VHDL FIFO
1
Readings
- Files for Week 2 Programming Assignments
1
Quiz
- Module 2 Quiz
Lectures
8
Videos
- Verilog for fun and profit (intro)
- Your First Verilog phrase
- Verilog Rules and Syntax; Keywords and Identifiers; Sigasi/Quartus editing
- Verilog Statements and Operators
- Verilog Modules, Port Modes and Data Types
- Verilog Structure
- Testing with ModelSim
- Verilog Evaluation
1
Readings
- Week 3 Readings
Week 3 Missions
- Verilog 2-bit Comparator
- Verilog Correct Errors
- Verilog Majority Vote
- Verilog 4-bit Full Adder
1
Videos
- Submitting Verilog Programming Assignments
1
Readings
- Files for Week 3 Programming Assignments
2
Quiz
- Verilog Find the Errors
- Module 3 Quiz
Lectures
10
Videos
- Learning to speak Verilog (intro)
- Combinatorial Circuits
- Synchronous Logic: Latches and Flip Flops
- Synchronous Logic: Counters and Registers
- Buses and Tristate Buffers
- Modular Design in Verilog
- Testbenches in Verilog
- Testbenches in Verilog II
- Memory with Verilog
- Verilog Finite State Machines
1
Readings
- Week 4 Readings
Week 4 Missions
- Verilog 74LS161 Binary Counter
- Verilog Make a Memory
- Verilog Finite State Machine
- Verilog ALU
- Verilog FIFO
1
Readings
- Files for Week 4 Programming Assignments
1
Quiz
- Module 4 Quiz

Instructors
Timothy Scherr

Instructors
Benjamin Spriggs