- Level Professional
- Duration 18 hours
- Course by University of Colorado Boulder
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Offered by
About
This course can also be taken for academic credit as ECEA 5360, part of CU Boulder's Master of Science in Electrical Engineering degree. Programmable Logic has become more and more common as a core technology used to build electronic systems. By integrating soft-core or hardcore processors, these devices have become complete systems on a chip, steadily displacing general purpose processors and ASICs. In particular, high performance systems are now almost always implemented with FPGAs. This course will give you the foundation for FPGA design in Embedded Systems along with practical design skills. You will learn what an FPGA is and how this technology was developed, how to select the best FPGA architecture for a given application, how to use state of the art software tools for FPGA development, and solve critical digital design problems using FPGAs. You use FPGA development tools to complete several example designs, including a custom processor. If you are thinking of a career in Electronics Design or an engineer looking at a career change, this is a great course to enhance your career opportunities. Hardware Requirements: You must have access to computer resources to run the development tools, a PC running either Windows 7, 8, or 10 or a recent Linux OS which must be RHEL 6.5 or CentOS Linux 6.5 or later. Either Linux OS could be run as a virtual machine under Windows 8 or 10. The tools do not run on Apple Mac computers. Whatever the OS, the computer must have at least 8 GB of RAM. Most new laptops will have this, or it may be possible to upgrade the memory.Modules
Introduction to the Course
1
Discussions
- Introduce Yourself
2
Videos
- Course Introduction
- Course Overview
3
Readings
- About This Course
- Hardware Requirements
- Introduction to FPGA Design for Embedded Systems Assessment Strategy
Introduction to the Module
1
Videos
- 1. Welcome to the world of programmable logic and FPGA design
1
Readings
- Week 1 Suggested Readings
FPGA Origins and Architecture
1
Discussions
- Look-up Tables vs. Gates
3
Videos
- 2. A Brief History of Programmable Logic
- 3. CPLD Architecture
- 4. LUTs and FPGA Architecture
Logic Design with FPGAs
3
Videos
- 5. LUTs for Logic Design
- 6. Designing Adders
- 7. Designing Multipliers
Week 1 Missions
1
Peer Review
- Mission 001: Week 1 Application Assignment
1
Readings
- Week 2 Assignment Instructions and Files
1
Quiz
- Mission 002: Week 1 Quiz
Introduction to the Module
1
Videos
- 1. The FPGA Design Flow
2
Readings
- Week 2 Suggested Readings
- Week 2 Required Reading and File Installation
FPGA Design with Quartus Prime
4
Videos
- 3. Installing Quartus Prime
- 4. Introducing Quartus Prime
- 5. Create a design project in Quartus Prime
- 6. Create a design in Quartus Prime
Executing FPGA Design Flow
5
Videos
- 7. Compile a Design
- 8. View the RTL
- 9. Timing Analysis with Time Quest I
- 10. Timing Analysis with Time Quest II
- 11. Simulate a design with ModelSim
Week 2 Missions
1
Peer Review
- Mission 004: Week 2 Application Assignment
2
Quiz
- Mission 003 : Practice Opportunity
- Mission 005: Week 2 Quiz
Introduction to the Module
1
Videos
- 1. Many types of FPGAs
1
Readings
- Week 3 Suggested Readings
FPGA Architectures: SRAM, FLASH, AND ANTI-FUSE
2
Discussions
- Intel/Altera MAX10
- FLASH Configuration Memory in Microsemi FPGAs
7
Videos
- 2. Xilinx CPLD Architecture
- 3. Xilinx Small FPGAs
- 4. Xilinx Large FPGAs
- 5. Altera CPLDs and Small FPGAs
- 6. Altera Large FPGAs
- 7. Microsemi Single-chip FPGA solutions
- 8. Lattice Single-Chip FPGA solutions
1
Readings
- Week 4 Assignment Instructions and Files
1
Quiz
- Mission 006: Week 3 Quiz
Introduction to the Module
1
Videos
- 1. FPGA Design Expertise
1
Readings
- Week 4 Suggested Readings
FPGA Design Techniques
1
Discussions
- Pipelines and IP blocks
3
Videos
- 2. Advanced Schematic Entry for FPGA Design- Drawing and Hierarchy
- 3. Improving Productivity with IP Blocks
- 4. Improving Timing with Pipelining
FPGA Interfacing
3
Videos
- 5. FPGA IO: Getting In and Getting Out
- 6. Pin Assignments: Making them Spot On!
- 7. Programming the FPGA
FPGA System Design
1
Peer Review
- Mission 007: Week 4 Application Assignment
3
Videos
- 8. Becoming one with Q: Qsys System Design
- 9.a Becoming one with Q Part II: Qsys System Design Finishing Touches
- 9.b Becoming one with Q Part III: Qsys System Design Finishing Touches
1
Quiz
- Mission 008: Week 4 Quiz

Timothy Scherr